1. Field Of The Invention
The present invention relates to the field of multiply-accumulators, and more particular, to the field of multiply-accumulators utilizing single-flux-quantum logic circuits.
2. Description of Related Art
High speed digital signal processing is becoming increasingly important for advanced electronic applications. High speed digital signal processing is crucial for the realization of digital bandpass interpolation filters for wide band rf systems. Josephson-junction based logic offers the potential for orders of magnitude improvement in both speed and power over equivalent semiconductor based circuits.
By utilization of a circuit architecture known as Modified Variable Threshold Logic (MVTL), an 8-bit processor was capable of operating at clock speeds of up to one gigahertz with 12 mW of power dissipation. In the MVTL circuit architecture, information is stored as voltages across Superconducting Quantum Interference Devices (SQUIDs). Although the performance of the MVTL circuit is impressive, such a circuit does not take full advantage of the inherent speed of Josephson junctions. The operating speed of MVTL circuits is limited by the use of latching gates which require an active reset in switching from a logical "ONE" to a logical "ZERO".
Recently, circuit designs for a logic family have been described in which the binary information is stored as magnetic flux in superconducting loops. Information is transmitted within such a circuit in the form of voltage pulses. Because a single-flux-quantum, .PHI..sub.0 (.PHI..sub.0 =2.07 mV.ps), is used to denote each binary "ONE", this circuit architecture is referred to as Rapid Single Flux Quantum (RSFQ) logic. Clock rates of up to 200 GHz have been projected for such circuits with orders of magnitude improvements in power dissipation over MVTL circuits. In addition, the operating margins of RSFQ circuits are larger than for comparable MVTL circuits.
In Likharev and Semenov, "RSFQ Logic/Memory: A New Josephson-junction Technology for Sub-Terahertz-Clock-Frequency Digital Systems," IEEE Trans. on Applied Superconductivity, Vol. 1, pp. 3-28 (March 1991) an RSFQ serial multiplier is disclosed which is formed of various logic elements including non-destructive readout (NDRO) cells, destructive readout (DRO) cells, and one-bit full adders (FA). A block diagram of this multiplier 10 is shown in FIG. 1.
To multiply two n-bit numbers, A and B, in multiplier 10 [A=(a.sub.n-1, a.sub.n-2, . . . , a.sub.0) and B=(b.sub.n-1, b.sub.n-2, . . . , b.sub.0)], the digits of B are first read into the NDRO cells 12 using a series of timing pulses T.sub.B. Each NDRO cell 12 will contain a separate bit of the B multiplicand. Multiplication is accomplished by multiplying each bit of the A multiplicand with the series of bits of the B multiplicand loaded into the NDRO cells 12. During such multiplication, the state of a.sub.i sets the DRO cells 14. If a.sub.i =1, a pulse is sent to the set inputs of the DRO cells 14. If a.sub.i =0, no pulse is sent. A timing pulse T.sub.A is used to read out the DRO cells 14, with the output (a.sub.i) triggering the NDRO cells 12 in the event a.sub.i =1. In this way, the partial product [p.sub.i =a.sub.i .times. B=(a.sub.i b.sub.n-1 +a.sub.i b.sub.n-2 +. . . +a.sub.i b.sub.0)] is generated in the string of full adders 16.
The pulse T.sub.A also outputs the sum bits of the full adders 16 to redirect the carry bits to inputs on the same adders. The DRO cells 14 are then set by the next bit (a.sub.1) of the A multiplicand and the procedure is repeated. At each pulse T.sub.A, one bit of the product (p.sub.i) emerges from the full adder 16 string. After 2n cycles, the multiplication is complete. Projected performance of multiplier 10 is 0.5 billion multiplications per second for 32-bit.times.32-bit multiplications.
While RSFQ logic offers high-speed and low-power operation, and although all of the required logic elements have been successfully modeled, this architecture still lacks a reliable single-bit full adder 16. Full adders 16 proposed to date have proved to have limited operating margins, particularly for reset. Since the one-bit full adder 16 is a basic building block of a serial multiplier 10, this poses a serious limitation. Consequently, there is a need for a serial multiplier which does not rely on a full adder cell which nevertheless offers the benefits of RSFQ digital processing with added reliability.